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Selective multiplexer-removal algorithm for lowering power consumption of circuits

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5 Author(s)
Chi-Hoon Shin ; Comput. Software & Eng., Univ. of Sci. & Technol. (UST), Daejeon ; Myeong-Hoon Oh ; Young-Woo Kim ; Sung-Nam Kim
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In this paper we propose an algorithm about aggressive, but partial removal of multiplexers used for sharing functional units (FUs). By eliminating some multiplexers and duplicating the FU related, the proposed algorithm could be more advantageous for low power circuits than just keeping the multiplexers. To determine whether a removal of a group of multiplexers is beneficial or not, we compared a FU with multiplexers to multiple replications of the FU without any multiplexer under various conditions. Through the experiments, we aggregated information to be used for finding appropriate multiplexers to be extricated from circuit netlist; using the information, we built an automated algorithm to remove particular multiplexers; we applied it to a netlist of 16 bit processor. The processor that is newly generated by the algorithm consumed average about 12% less power than the initial processor.

Published in:

SoC Design Conference, 2008. ISOCC '08. International  (Volume:02 )

Date of Conference:

24-25 Nov. 2008