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A new design method to reduce the power consumption in a flash-A/D converter

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4 Author(s)
Soon-Ik Cho ; Dept. of Electr. Eng., Korea Univ., Seoul ; Soon-Kyung Choi ; Suki Kim ; Kwang-Hyun Baek

In this paper, we propose a new design method to control the clock duty ratio of a flash-A/D converter. Using this method, the power consumption of comparators in an A/D converter can be reduced drastically with very few additional circuits. Digital back-end including error-correction and encoding block also have more time to treat data from comparators due to being extended data length. Additionally, we can reduce the area of comparators and digital back-end. Simulation results show that the power consumption of a comparator using clock which has a duty ratio of 0.25 is more efficient by about 50% compared to a comparator which uses clock with a duty ratio of 0.5.

Published in:

SoC Design Conference, 2008. ISOCC '08. International  (Volume:02 )

Date of Conference:

24-25 Nov. 2008