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A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder

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2 Author(s)
Yuan-Chun Lin ; Dept. of Comput. Sci., Nat. Tsing HuaUniversity, Hsinchu ; Youn-Long Lin

We propose a high-performance hardwired deblocking filter for H.264/AVC decoding. To decode QFHD (3840 times 2160, i.e., four times full HD) ultra high definition video, we minimize number of processing cycles, working frequency and amount of external memory traffic. We propose a novel filtering order and employ a 5-stage pipelined and resource-shared dual-edge filter to generate two filtering results every cycle. Taking advantage of skip modes, our filter takes only 48 cycles to filter a macroblock in the best case and 100 in the worst case. Furthermore, it eliminates most unnecessary off-chip memory traffic with a novel on-chip memory scheme. Our design can support QFHD at 30 fps application by running only at 98 MHz.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:17 ,  Issue: 6 )

Date of Publication:

June 2009

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