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Tate-pairing-based cryptosystems, because of their ability to be used in multiparty identity-based key management schemes, have recently emerged as an alternative to traditional public key cryptosystems. Due to the inherent parallelism of the existing pairing algorithms, high performance can be achieved via hardware realizations. Three schemes for Tate pairing computations have been proposed in the literature: cubic elliptic, binary elliptic, and binary hyperelliptic. In this paper, we propose a new FPGA-based architecture of the Tate-pairing-based computation over binary fields. Even though our field sizes are larger than in the architectures based on cubic elliptic curves or binary hyperelliptic curves with the same security strength, nevertheless fewer multiplications in the underlying field need to be performed. As a result, the computational latency for a pairing computation has been reduced, and our implementation runs 2-20 times faster than the equivalent implementations of other pairing-based schemes at the same level of security strength. Furthermore, we ported our pairing designs for eight field sizes ranging from 239 to 557 bits to the reconfigurable computer, SGI Altix 4700 supported by Silicon Graphics, Inc., and performance and cost are demonstrated.
Date of Publication: Sept. 2009