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Test Structures Utilizing High-Precision Fast Testing For 32nm Yield Enhancement

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3 Author(s)
Karthikeyan, M. ; IBM Syst. & Technol. Group, Hopewell Junction, NY ; Medina, L. ; Shiling, E.

We describe the development and use of various test structures for 32 nm yield enhancement. These DC defect test structures are tested in parallel mode on a functional tester using special V/I and Pico-Amp measurement cards. This new test method provides measurement accuracy as high as plusmn10 pA along with up to 9times reduction in test time over conventional parametric testing. The large critical area enables reliable estimation of defect densities by failure mechanism.

Published in:

Microelectronic Test Structures, 2009. ICMTS 2009. IEEE International Conference on

Date of Conference:

March 30 2009-April 2 2009