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DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In

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5 Author(s)
Wei-Chung Kao ; Electr. Eng. Dept., Nat. Taiwan Univ., Taipei, Taiwan ; Wei-Shun Chuang ; Hsiu-Ting Lin ; Li, J.C.-M.
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This paper presents a design for testability and minimum leakage pattern generation technique to reduce static power during test and burn-in for nanometer technologies. This technique transforms the minimum leakage pattern generation problem into a pseudo-Boolean optimization (PBO) problem. Nonlinear objective functions of leakage power are approximated by linear ones such that this problem can be solved efficiently by an existing PBO solver. A partitioning-based algorithm is applied for control point insertion and also CPU time reduction. Experimental results on the IEEE ISCAS'89 benchmark circuits using Taiwan Semiconductor Manufacturing Company 90-nm technology show that, for large circuits, the static power is reduced from 8.3% (without partition) to 17.47% (with 64 partitions). Besides, the overall CPU time is reduced from 3600 s (without partition) to 83 s (with 64 partitions). This technique reduces the static power without changing the manufacturing process or library cells.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 3 )

Date of Publication:

March 2010

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