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Single error correctable bit parallel multipliers over GF(2m)

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4 Author(s)
Mathew, J. ; Dept. of Comput. Sci., Univ. of Bristol, Bristol ; Jabir, A.M. ; Rahaman, H. ; Pradhan, D.K.

Motivated by the problems associated with soft errors in digital circuits and fault-related attacks in cryptographic hardware, a systematic method for designing single error correcting multiplier circuits is presented for finite fields or Galois fields over GF(2m). Multiple parity predictions to correct single errors based on the Hamming principles are used. The expressions for the parity prediction are derived from the input operands, and are based on the primitive polynomials of the fields. This technique, when compared with existing ones, gives better performance. It is shown that single error correction (SEC) multipliers over GF(2m) require slightly over 100% extra hardware, whereas with the traditional SEC techniques, this figure is more than 200%. Since single bit internal faults can cause multiple faults in the outputs, this has also been addressed here by using multiple Hamming codes with optimised hardware.

Published in:

Computers & Digital Techniques, IET  (Volume:3 ,  Issue: 3 )

Date of Publication:

May 2009

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