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Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problems

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2 Author(s)
Rice, J.E. ; Dept. of Math & Comput. Sci., Univ. of Lethbridge, Lethbridge, AB ; Kent, K.B.

Reconfigurable hardware has recently shown itself to be an appropriate solution to speeding up problems that are highly dependent on a particular complex or repetitive sub-algorithm. In most cases, these types of solutions lend themselves well to parallel solutions. The optimal design on field programmable gate arrays (FPGAs) for problems with algorithms or sub-algorithms that can be highly parallelised is investigated. In addition, a classification system is introduced, which categorises FPGA-based solutions into 'instance-specific' and 'parameter-specific'.

Published in:

Computers & Digital Techniques, IET  (Volume:3 ,  Issue: 3 )

Date of Publication:

May 2009

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