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Execution time reduction of Differential Power Analysis experiments

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3 Author(s)
Giorgio Di Natale ; Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université Montpellier II / CNRS UMR 5506, 161 rue Ada, 34392 Cedex 5, France ; Marie-Lise Flottes ; Bruno Rouzeyre

Cryptographic devices can be subject to side-channel attacks that consist in retrieving secret data by observing physical properties of the device. Among those attacks, differential power analysis (DPA) has proven to be very effective and easy to perform. Several countermeasures have been proposed in the literature and one of the most promising is based on power balanced design. There are still not known methods for manufacturing test of power balanced circuits, aside from performing full DPA. This paper proposes a novel method that allows to drastically reduce the number of input vectors used for the DPA, thus reducing the overall test time.

Published in:

2009 10th Latin American Test Workshop

Date of Conference:

2-5 March 2009