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Advancing technology has made it possible to integrate millions of transistors on a very small die and to clock these transistors at very high speeds. Power consumption has become the limiting factor for portable high-performance wireless applications. In this paper, we propose a system level technique to improve the power efficiency of the wireless receiver design. The proposed clock gating scheme utilizing carrier sensing based on cross-correlation is a very effective power-saving technique to reduce the dynamic power dissipation of the inactive circuit blocks and their local clock buffers.
Date of Conference: 15-17 Dec. 2008