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Digital error correction technique for binary decision successive approximation ADCs

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4 Author(s)

A digital error correction technique with negligible hardware overhead is proposed for binary successive approximation ADCs. A redundant decision phase is inserted between the normal SAR operations, and the coarse decision error caused by incomplete DAC settling is corrected by a digital code addition. The relaxed DAC settling requirement for coarse decision increases the conversion speed.

Published in:

Electronics Letters  (Volume:45 ,  Issue: 8 )