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Data path synthesis in digital electronics. II. Bus synthesis

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1 Author(s)
C. H. Chen ; Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

For pt. I see ibid., vol. 32, no. 1, p. 1-15 (1996). Common buses are an extremely efficient structure for achieving area minimization so that the bus-oriented interconnection of registers and data operators plays an important role in data path synthesis. The overriding design goal is efficiently allocating the minimum number of buses and gating elements (i.e. multiplexers) for achieving communication between the data path elements. New efficient algorithms for the automated allocation of buses in data paths have been developed. The entire allocation process can be formulated as a graph partitioning problem. This formulation readily lends itself to the use of a varieties of heuristics for solving the allocation problem We present efficient algorithms which provide excellent solutions to this formulation of the allocation problem The operation of the algorithms is clearly demonstrated using detailed examples.

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IEEE Transactions on Aerospace and Electronic Systems  (Volume:32 ,  Issue: 1 )