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We report on the performance of a low noise and high count rate readout ASIC with binary architecture and energy window selection for X-ray imaging applications using semiconductor detectors. The ASIC called RG64 is designed in 0.35 mum CMOS process and its total area is 3900times5000 mum2. The core of RG64 consists of 64 readout channels. Each channel is built of a charge sensitive amplifier with a second order shaper of peaking time 75 ns, two independent discriminators with an 8-bit offset correction circuit and two independent 20-bit counters with RAM memory buffers. The ENC of the circuit reaches the value of about 126 el. rms with 1 pF input load and 5 mW power consumption per single channel. The mean gain in the multichannel ASIC is about 50 muV/el., with the dispersion from channel to channel of 0.9% (on one sigma level). The deviation of the effective threshold voltage spread for given energy can be reduced to less than 7 el. rms (calculated to the charge sensitive amplifier input). High count rate measurements have been performed up to 2 Mcps of average rate of input pulses, both for AC and DC coupled silicon strip detectors with X-ray photons of energy 8.04 keV. The RG64 can operate both in the continuous readout mode and in the readout mode separate from exposure.