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Analysis and Design of a Robust Floating Point CMOS Image Sensor

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3 Author(s)
Jehyuk Rhee ; MagnaChip Semicond., Inc., Lake Oswego, OR ; Dongwon Park ; Youngjoong Joo

A robust floating point CMOS image sensor (CIS) is designed and tested. A detailed analysis for signal-to-noise ratio (SNR) of the floating point CIS including the effect of the exponent detection error is presented. Based on the analysis, a simple way to effectively remove the optimum integration time detection error is proposed. In addition, the proposed imager obtains the exponent at the beginning of the image capturing cycle, which provides a logarithmic image of the scene. A 32 times 24 prototype sensor including 4 transistors pixel array, 4 bit static random access memory (SRAM) array, 8 bit ADC and CDS block, and integration time control block was designed and fabricated using standard 0.5 mum CMOS process. It achieved 50.5 dB of dynamic range (DR) enhancement with 32 dB of peak SNR at 30 frames/s.

Published in:

IEEE Sensors Journal  (Volume:9 ,  Issue: 5 )