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Mitigation Techniques for Single-Event-Induced Charge Sharing in a 90-nm Bulk CMOS Process

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12 Author(s)
Amusan, O.A. ; Electr. Eng. & Comput. Sci. Dept., Vanderbilt Univ., Nashville, TN ; Massengill, L.W. ; Baze, M.P. ; Bhuva, B.L.
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In this paper, mitigation techniques to reduce the increased SEU cross section associated with charge sharing in a 90-nm dual-interlocked-cell latch are proposed. The increased error cross section is caused by heavy-ion angular strikes depending on the direction of the ion strike, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal spacing as a mitigation technique shows an order of magnitude decrease on upset cross section as compared to a conventional layout, and the use of guard-rings show no noticeable effect on upset cross section.

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Device and Materials Reliability, IEEE Transactions on  (Volume:9 ,  Issue: 2 )