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Optimizing Inverse-Mode SiGe HBTs for Immunity to Heavy-Ion-Induced Single-Event Upset

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3 Author(s)
Appaswamy, A. ; Georgia Inst. of Technol., Atlanta, GA ; Phillips, S. ; Cressler, J.D.

Inverse-mode (collector-up) operation is proposed as a solution to the single-event-upset susceptibility observed in commercially available bulk silicon-germanium heterojunction bipolar transistors. Inverse-mode performance optimization techniques, which require no process changes or added lithographic masks, are demonstrated, yielding inverse-mode transistor performance capable of supporting gigabit-per-second digital logic needed in space-based communication systems.

Published in:

Electron Device Letters, IEEE  (Volume:30 ,  Issue: 5 )