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Electroplated Metal Buried Interconnect and Through-Wafer Metal-Filled Via Technology for High-Power Integrated Electronics

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6 Author(s)
Chang-Hyeon Ji ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Herrault, F. ; Hopper, P. ; Smeys, P.
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In this paper, we present the design, fabrication process, and experimental results of an electroplated metal buried interconnect and through-wafer via technology suitable for extremely low resistance interconnection of microelectronic devices. The technology is demonstrated using a 3-D daisy-chain test structure comprised of electroplated through-wafer vias buried in the silicon substrate to form the respective interconnect. In contrast to the conventional daisy-chain structures used in flip chip joining and packaging, the designed structure is fabricated on a single substrate without requiring a subsequent bonding process. The top connectors formed on the front-side of the substrate are connected to bottom connectors buried inside the substrate (buried interconnects) through 61-mum-high, void-free, fully-filled, electroplated vias. The metal electroplated buried interconnects are fabricated at the bottom surface of 232-mum-deep trenches formed on the backside of the substrate. Processes for forming deep trenches with rounded-off edges and photoresist spray coating have been developed to fabricate the buried interconnects and complete the daisy-chain structure. Developed processes enable conformal photoresist deposition inside the deep vertical trenches with excellent step and sidewall coverage, surpassing the limitations of conventional fabrication approaches. Furthermore, electroplating molds were perfectly patterned at the bottom of these deep trenches. Through-wafer vias with controllable height are fabricated by direct bottom-up plating from the buried interconnect without additional preparation, such as wafer bonding or hole filling processes. The interconnection scheme developed in this research considerably reduces the height of narrow vertical vias, compared to conventional through-wafer vias, and enables a high density array of interconnect structures. Moreover, low resistance interconnect suitable for high power applications can be realized with thick el- - ectroplated copper and fully-filled vias. Buried interconnect can be also utilized in high voltage transistor applications. Resistance testing has been performed to validate the electrical integrity of the fabricated daisy-chain structure, and the results are compared with simulation and analytical calculations.

Published in:

Advanced Packaging, IEEE Transactions on  (Volume:32 ,  Issue: 3 )

Date of Publication:

Aug. 2009

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