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This paper presents several efficient architectures of dynamic/static edge-triggered flip-flops with a compact embedded logic. The proposed structure, which benefits from the overlap period, fixes most of the drawbacks of the dynamic logic family. The design issues of setting the appropriate overlap period for this architecture are explained. The proposed overlap-based approach is compared with several state-of-the-art dynamic/static logic styles in implementing a 4-bit shift register and an odd-even sort coprocessor using different CMOS technologies. The simulation results showed that the overlap-based logic cells become much more efficient when the complexity of their embedded logic function increases. Moreover, this approach improves static power consumption, which makes it even more efficient in below 0.18 ??m CMOS technologies.