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Self-Repairing SRAM Using On-Chip Detection and Compensation

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5 Author(s)
Mojumder, N.N. ; Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Mukhopadhyay, S. ; Jae-Joon Kim ; Ching-Te Chuang
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In nanometer scale static-RAM (SRAM) arrays, systematic inter-die and random within-die variations in process parameters can cause significant parametric failures, severely degrading parametric yield. In this paper, we investigate the interaction between the inter-die and intra-die V t variations on SRAM read and write failures. To improve the robustness of the SRAM cell, we propose a closed-loop compensation scheme using on-chip monitors that directly sense the global read stability and writability of the cell. Simulations based on 45-nm partially depleted silicon-on-insulator technology demonstrate the viability and the effectiveness of the scheme in SRAM yield enhancement.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 1 )

Date of Publication:

Jan. 2010

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