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In this paper, an efficient parallel flow for the design of the full power distribution network (PDN) is proposed. The analysis demonstrates the impact of the voltage regulator model in both frequency and time domain response. Based on the experimental results, it is observed that including the voltage regulator model in the PDN model increases the transient voltage drop and PDN response which need to be considered for nanoscale ICs. The flow is optimized using parallel processing to speedup slow response simulation time of the off chip voltage regulator. The study highlights the power integrity issues related to voltage regulator in broadband frequency ranges. The experimental results show speedup of up to 22 times with single processor and more than 430 times using up to 200 processors compared to HSPICE and other commercial simulators. The PDN simulation time is reduced from hours to less than a minute.