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As CMOS technology feature sizes decrease, random within-die and inter-die process variations more and more jeopardize SoC parametric and functional yield. Largely neglected in the state-of-the-art, dynamic energy consumption and power dissipation becomes heavily affected. This paper describes a technique to systematically bring statistically correlated timing/energy variations all the way up from the device to the SoC level. We propose a flow for variability aware modeling (VAM) and apply it to a case study using a industrial test vehicle.