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We explore two schemes using transmission-line (T-line) to achieve high-performance global interconnects on VLSI chips. For both schemes, we select wire dimensions to ensure T-line effects present and employ inverter chains as drivers and receivers. In order to achieve high throughput and alleviate Inter-Symbol Interference (ISI), high termination resistance is used in the second scheme. For the two schemes, we discuss how to optimize the wire dimensions and the effects of driver impedance and termination resistance on the wire bandwidth. Secondly, design methodology is proposed to determine the optimal design variables for three objectives. We adopt the proposed methodology and compare the performance metrics with repeated RC wires. Simulation results show that, the proposed T-line schemes reduce the delay and improve the throughput as much as 82% and 63%, for min-ddp (delay2-power product) objective.