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An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs

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4 Author(s)

SoC verification efforts involve multiple models of the design - RTL, FPGA, silicon and software models. With increasing design complexity, re-use of tests between models is a must. In this paper, we introduce a stimulus abstraction mechanism which greatly increases the re-usability of tests across models. We then demonstrate an implementation of the abstraction mechanism on two models of a PCI-express based design. Identical tests are used to drive an RTL model via a BFM and a software model via stream sockets to achieve the same result.

Published in:

Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design

Date of Conference:

16-18 March 2009

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