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Performance evaluation of wireless networks on chip architectures

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5 Author(s)
Ganguly, A. ; Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA ; Chang, K. ; Pande, P.P. ; Belzer, B.
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The performance benefits of conventional Network-on-Chip (NoC) architectures are limited by the high latency and energy dissipation in long distance multihop communication between embedded cores. To alleviate these problems, wireless on-chip networks are envisioned. Using miniaturized on-chip antennas as an enabling technology, wireless NoCs (WiNoCs) can be designed. In this paper we elaborate on the design methodology and technology requirements for a WiNoC and evaluate its performance. It is demonstrated that a WiNoC outperforms its wireline counterpart in terms of network throughput and latency, and that energy dissipation improves by an order of magnitude.

Published in:

Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design

Date of Conference:

16-18 March 2009