Cart (Loading....) | Create Account
Close category search window
 

Incremental power optimization for multiple supply voltage design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Yuchun Ma ; Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing ; Xiang Qiu ; Xiangqing He ; Xianlong Hong

Multiple supply voltage (MSV) is an effective method to optimize the chip power consumption. In MSV design, the voltage island is a crucial concern that the blocks with the same voltage level are clustered into one or more voltage islands to reduce the costs of voltage supply network and level converter. The distribution of voltage islands depends on not only the feasible voltage assignment based on timing analysis, but also the physical adjacency between blocks. In traditional post-floorplan voltage island generation approaches, the fixed layout of blocks limits the power optimization greatly. Instead of a start-over of searching process to generate better solutions, which suffers from long run time and poor scalability, in this paper, we propose an incremental power optimization methodology to further optimize the power consumption of traditional post-floorplan MSV design without compromising the circuit performance. A net-flow based timing slack distribution algorithm is proposed to obtain maximal power reduction, considering both the characters of each block and the circuit topology. Then we incrementally change the floorplan to re-construct the voltage island distribution based on the physical constraint graph, while the chip area, the total wire length and the performance are considered simultaneously. The experimental results show that our methodology can reduce the power consumption while the chip area, the total wire length and the power supply network cost are maintained at the same time.

Published in:

Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design

Date of Conference:

16-18 March 2009

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.