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Due to the notable change of channel width, supply voltage; and clock frequency, CMOS IC technologies are rapidly approaching their ultimate limits. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result in unacceptable error rates and make further nanometer scaling increasingly difficult. The error detection scheme based on GRAAL architecture (Global Reliability Architecture Approach for Logic) combines latch-based design and time redundancy techniques to achieve high detection efficiency for temporary faults (timing faults, SEUs, and SETs) at low area, power and speed penalties. In this paper, we use a finite state machine (FSM) circuit as test vehicle to validate the error detection architecture. The experimental results validate the claimed high error detection efficiency.
Date of Conference: 16-18 March 2009