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We propose a novel design flow for mismatch and process variation aware optimization of nanoscale CMOS active pixel sensor (APS) arrays. As a case study, an 8 times 8 APS array is designed using the proposed methodology for 32 nm CMOS technology. Performance metrics such as power, output voltage swing, dynamic range (DR) and capture time (delay) have been measured. The baseline results show a power consumption of 16.32 muW, output voltage swing of 428 mV, dynamic range (DR) of 59.47 dB and a capture time of 5.65 mus. The baseline APS array is subjected to 5% "intra-pixel" mismatch and 10% "inter-pixel" process variation and the effect on power and output voltage swing has been observed. The APS array is subjected to a design and analysis of Monte Carlo experiments based optimization. Using this approach, we have been able to achieve 21% reduction in power (including leakage). To the best of our knowledge, this is the first ever nano-CMOS implementation of an APS array optimized to be mismatch and process variation tolerant.