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New subthreshold concepts in 65nm CMOS technology

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6 Author(s)
Moradi, F. ; Dept. of Inf., Univ. of Oslo, Oslo ; Wisland, D.T. ; Mahmoodi, H. ; Peiravi, A.
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In this paper challenges observed in 65 nm technology for circuits utilizing subthreshold region operation are presented. Different circuits are analyzed and simulated for ultra low supply voltages to find the best topology for subthreshold operation. To support the theoretical discussions different topologies are analyzed and simulated. Various aspects of flip-flop circuits are described in detail to study which topology would be most suitable for ultra low supply voltage and low-power applications. Simulation results show that the power consumption decreases by at least 23% compared with other flip-flops. Also, the setup time and the hold time are improved.

Published in:

Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design

Date of Conference:

16-18 March 2009