Cart (Loading....) | Create Account
Close category search window
 

Architecture design exploration of three-dimensional (3D) integrated DRAM

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Anigundi, R ; Rensselaer Polytech. Inst., Troy, NY ; Hongbin Sun ; Jian-Qiang Lu ; Rose, K.
more authors

Motivated by increasingly promising three-dimensional (3D) integration technologies, this paper reports an architecture design of 3D integrated dynamic RAM (DRAM). To accommodate the potentially significant pitch mismatch between DRAM word-line/bit-line and through silicon vias (TSVs) for 3D integration, this paper presents two modestly different coarse-grained inter-sub-array 3D DRAM architecture partitioning strategies. Furthermore, to mitigate the potential yield loss induced by 3D integration, we propose an interdie inter-sub-array redundancy repair approach to improve the memory repair success rate. For the purpose of evaluation, we modified CACTI 5 to support the proposed coarse-grained 3D partitioning strategies. Estimation results show that, for the realization of a 1 Gb DRAM with 8 banks and 256-bit data I/O, such 3D DRAM design strategies can effectively reduce the silicon area, access latency, and energy consumption compared with 3D packaging with wire bonding and conventional 2D design. We further developed a memory redundancy repair simulator to demonstrate the effectiveness of proposed inter-die inter-subarray redundancy repair approach.

Published in:

Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design

Date of Conference:

16-18 March 2009

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.