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Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design

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5 Author(s)

We describe here, the design and use of a unique test chip on power and variability (TPV) to measure and report for the first time, the magnitude of leakage and dynamic power dissipation and its variation. This test chip, fabricated in a state-of-the-art 45 nm process node technology, addresses the important issues of variability in power and delay and quantifies them as a function of voltage and cycle time. Multiple power-saving techniques are implemented on-chip to facilitate the analysis. The uniqueness of the chip lies in: a) the use of 64 AES core-based processing-element (PE) blocks that are identical, independently controllable and designed using a state-of-the-art power-aware design flow, b) the use of MTCMOS switches within each PE block combined with multiple power domains which results in excellent granularity of power measurements and, c) the implementation of separate voltage areas in each PE block which enables power measurements down to very low voltages. Good correlation was established between measured data and simulations. Estimates of within-die and die-to-die delay variability were also quantified through measurements of Vddmin, the minimum voltage for functionality. For the silicon tested, the analysis of Vddmin revealed significant within-die variations which were similar in magnitude to the die-to-die variations seen. A methodology to use the Vddmin variation to estimate on-chip delay variability is described in detail.

Published in:

Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design

Date of Conference:

16-18 March 2009

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