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This paper presents an integrated modeling, simulation and analysis technique for high-speed serial link transceiver over band-limited channel. The Verilog-A behavioral modeling blocks, transistor-level circuits based on the BSIM models, and the backplane channel with .s4p format model were simulated simultaneously in Cadence Spectre environment. The output data were post-processed with Matlab for performance analysis. Compared with HDL-based modeling scheme and event-driven modeling method, the proposed modeling method provides the effective system level verification in the integrated environment, even with real transistor-level circuits included.