Greedy Dynamic Crossover Management in Hardware Accelerated Genetic Algorithm Implementations Using FPGA

Genetic algorithms are robust parallel calculation methods based on natural selection. Various crossover and mutation methods to accomplish Genetic Algorithm (GA), namely, single point, multipoint, uniform, greedy, migration, and on-demand etc.; exist. However, these mechanisms are static in nature. This paper presents a dynamic crossover (DC) mechanism. We investigate its performance by implementing in hardware (FPGA) with convergence rate and higher fitness as the performance metric. The purpose of the DC concept is two fold; to achieve faster convergence and to consume lesser memory by keeping the population size static. The results indicate that for a linear and a nonlinear objective function, DC outperforms all static crossover mechanisms.