By Topic

Optimization of Bank Switching Instructions in Embedded Systems through Static Analysis of Machine Codes

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chacko, M. ; Dept. of Ship Technol., Cochin Univ. of Sci. & Technol., Cochin ; Jacob, P.

This paper describes a static machine code analyzer which helps to eliminate the redundant bank switching instructions in partitioned memory architectures. Our approach rests on a state transition diagram representing the memory bank switching corresponding to each bank selection instruction. Redundant data memory bank selection instructions in the intraprocedural sequence, loops and interprocedural routines in the application program are eliminated. Analysis is done at machine code levels, so no software or runtime overhead. This results in reduced code size as well as increased execution speed. No assertion or annotated assembly code is needed. This method scales well into large number of memory blocks as well as other architectures, once appropriate information is available. A prototype based on PIC 16F87X microcontrollers is described. A detailed algorithm is prescribed in this paper.

Published in:

Advance Computing Conference, 2009. IACC 2009. IEEE International

Date of Conference:

6-7 March 2009