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Performance modeling of a network processor data path using Queuing Systems

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3 Author(s)
Manivannan Kolendavelu ; Wireline Communications Department, Infineon Technologies Pvt. Ltd., Bangalore, India ; Satish Polisetti ; Raimar Thudt

Requirement of performance modeling during the early SoC design stages becomes increasingly important to take major system level decisions relating to hardware resources, mapping of functionality onto computing modules and selection of scheduling algorithms which affects the design significantly. In this work, we make use of queuing systems to model the data path of network processors to decide on the internal and external memory requirements of an ASIC or SoC. We propose a framework developed using System-C, which can be used for performance modeling & simulations of network processing engines. The real time Internet traffic patterns seen across US and Japan are used to stimulate our performance model. We also demonstrate how the packet length distribution across US and Japan demands different memory requirements in the architecture of the network processor. Leveraging on real time Internet traces unlike simulating using standard Internet MIX approximations, our methodology has an additional advantage of optimizing the SoC architectures based on the region it is being targeted. This results in an optimized architecture which saves the chip area, chip cost, data processing times and memory size requirements without compromising on the throughput requirements.

Published in:

2009 First International Communication Systems and Networks and Workshops

Date of Conference:

5-10 Jan. 2009