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System-level Built-In Self-Test of global routing resources in Virtex-4 FPGAs

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4 Author(s)
Jia Yao ; Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL ; Dixon, B. ; Stroud, C. ; Nelson, V.

We describe the implementation of a cross-coupled parity built-in self-test (BIST) approach for the global routing resources in field programmable gate arrays (FPGAs). The BIST approach facilitates system-level testing of the FPGA global routing resources prior to configuring the intended system function for high reliability/availability systems. We discuss the application of the BIST approach to the global routing resources in Xilinx Virtex-4 FPGAs including experimental results of implementations in actual devices.

Published in:

System Theory, 2009. SSST 2009. 41st Southeastern Symposium on

Date of Conference:

15-17 March 2009