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Low power and area efficient image segmentation VLSI architecture using 2-dimensional pixel-block scanning

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5 Author(s)
Okazaki, K. ; Grad. Sch. of Adv. Sci. of Matter, Hiroshima Univ., Higashi-Hiroshima ; Nagaoka, N. ; Sugahara, T. ; Koide, T.
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We report a pixel-block scanning image segmentation VLSI based on a region-growing approach. Using the two techniques of (i) a limited scan to the boundary of each grown region and (ii) continued block-internal region growing, we have improved the overall segmentation speed and power consumption in comparison to a previous design. We evaluated the segmentation performance by MATLAB simulation and an ASIC design. The scan block shape and size are scalable, and can be optimized to fulfill segmentation speed, power consumption, and implementation area requirements. The pixel-parallel segmentation unit area could be reduced to 1/10 by changing the pixel-block size from 80 times 2 pixels to 4 times 4 pixels, which still enables real-time segmentation performance.

Published in:

Intelligent Signal Processing and Communications Systems, 2008. ISPACS 2008. International Symposium on

Date of Conference:

8-11 Feb. 2009