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A DLL Design for Testing I/O Setup and Hold Times

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2 Author(s)
Cheng Jia ; Electr. & Comput. Eng. Dept., Georgia Inst. of Technol., Atlanta, GA, USA ; Milor, L.

A built-in self-test (BIST) circuit has been designed to test setup and hold times of I/O registers or buffers for memory interfaces. This method enables independent testing of setup and hold times without using an external tester, except to generate the reference clock. The circuit uses a delay-locked loop (DLL) to generate delayed clocks. It has been implemented with a 0.18-mum TSMC process (CM018). The accuracy in delay generation is within 40 ps, for delay measurements ranging from 300 to 700 ps. In order to achieve high accuracy, the BIST circuit requires frequency adjustment during test, combined with averaging over multiple test cycles. To do this in an efficient manner, the DLL in the BIST circuit has been designed for a wide lock range, from 150 to 400 MHz, and achieves lock in less than 0.05 mus. This paper describes the design in detail and evaluates its performance, together with test time and accuracy. It also shows how to use a low-resolution DLL to achieve high accuracy through frequency adjustment and averaging over multiple test cycles.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:17 ,  Issue: 11 )