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Programmable Architecture for Flexi-Mode QC-LDPC Decoder Supporting Wireless LAN/MAN Applications and Beyond

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6 Author(s)
Dan Bao ; State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China ; Bo Xiang ; Rui Shen ; An Pan
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A programmable architecture is proposed for a flexi-mode quasi-cyclic low-density parity-check code decoder. The proposed architecture has the following advantages: 1) Code rate, length, and pattern can be programmed on the fly; 2) decoding complexity is reduced by algorithm modification; 3) memory read/write operation is reduced by access optimization and hierarchical memory structure; and 4) an early stopping scheme is adopted to give power efficiency, particularly in the low-signal-to-noise-ratio region. A decoder chip is implemented in an SMIC 180-nm 1.8-V CMOS technology. Experimental results show the advantages in terms of flexibility, area, power, and error-correction performance.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:57 ,  Issue: 1 )