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Robust Wafer-Level Thin-Film Encapsulation of Microstructures using Low Stress PECVD Silicon Carbide

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5 Author(s)
Rajaraman, V. ; Electron. Instrum. Lab., Delft Univ. of Technol., Delft ; Pakula, L.S. ; Pham, H.T.M. ; Sarro, P.M.
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This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide variety of surface- and thin-SOI microstructures that included microcavities, RF switches and various accelerometers. Advantages of our technique are its versatility, smaller footprint, reduced chip thickness and process complexity, post-CMOS batch processing capability and added functionality due to the possibility of integrating additional electrodes for MEMS. Besides fabrication details, this work also discusses related design aspects for large-area MEMS and demonstrates the encapsulation results. Successfully encapsulation of device geometries as large as 955times827 mum2 has been achieved.

Published in:

Micro Electro Mechanical Systems, 2009. MEMS 2009. IEEE 22nd International Conference on

Date of Conference:

25-29 Jan. 2009