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The Doherty amplifier was first proposed to improve the efficiency under output power back-off using the technique of load-line modulation of a dasiacarrierdasia amplifier through a dasiapeakdasia amplifier. By varying input bias of the peak amplifier along with load of the carrier amplifier at low drive levels, different topologies of the Doherty amplifier are distinguished. An analytical analysis that determines the optimum output performance of these topologies in terms of output power, efficiency and output power back-off ensuring a near-peak efficiency is developed. The presented comprehensive analysis considered for variation of conduction angle of the peak amplifier biased class C. New design equations of the analysed topologies are derived. A realisation at a central frequency of 1.9 GHz using GaAs field effect transistor (FET) devices of a Doherty amplifier topology is reported. In this topology the carrier operates (at low drive levels) into load impedance 5/2 times larger than its optimum. Power-added efficiency of 61.8 is measured at P 1dB of 25.9 dB m and 33.2 is measured at 9 dB back-off from P 1dB.