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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

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21 Author(s)
Klim, P.J. ; Syst. & Technol. Group, IBM, Austin, TX ; Barth, J. ; Reohr, W.R. ; Dick, D.
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We describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation , a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair control, on-chip OTPROM programming voltage generation, clock generation and distribution, array built-in self-test circuitry (ABIST), user logic and pervasive logic. The eDRAM employs a programmable pipeline, achieving 1.8 ns latency, and features concurrent refresh capability.

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Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 4 )