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The design and experimental results of a low-power, low-area 5-tap decision feedback equalizer (DFE) implemented in a 45 nm SOI CMOS technology are reported. The DFE employs a low-power current-integrating summer with sampling front-end, which eliminates systematic frequency-dependent loss inherent in conventional integrating serial receivers. Further power and area savings are achieved through the use of a direct-feedback architecture and CMOS-style rail-to-rail clocking. The 5-tap DFE core occupies 73 times 50 mum2 and consumes 11 mW from a 1 V supply when equalizing 12 Gb/s data passed over a 30" channel with 15 dB of loss at 6 GHz.