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A 0.7 V Single-Supply SRAM With 0.495 \mu m ^{2} Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

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10 Author(s)
Keiichi Kushida ; Center for Semicond. Res. & Dev., Toshiba Corp., Kawasaki ; Azuma Suzuki ; Gou Fukano ; Atsushi Kawasumi
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We proposed a novel SRAM architecture with a high-density cell in low-supply-voltage operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mum2 cell in 65 nm CMOS technology demonstrated 0.7 V single-supply operation.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:44 ,  Issue: 4 )