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A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification

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3 Author(s)
Hu, J. ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA ; Dolev, N. ; Murmann, B.

A low-power pipelined ADC featuring dynamic source follower amplifiers is presented in this paper. The proposed dynamic source follower-based architecture provides a low-power alternative to the traditional opamp-based MDAC circuits. This new type of circuit dynamically charges its load capacitance without a large bias current, leading to significant power savings. The presented ADC includes a low-power comparator with offset calibration and uses digital calibration for gain correction. Measured results indicate that the 9.4-bit, 50-MS/s prototype ADC achieves an SNDR of 49.2 dB (7.9 ENOB) and consumes 1.44 mW from a 1.2-V supply, resulting in a figure of merit of 119 fJ/conversion-step. The converter's input capacitance is 90 fF and the total active area is 0.123 mm2 in a 90 nm CMOS process.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 4 )