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In this paper, a low power 6-bit ADC that uses reference voltage and common-mode calibration is presented. A method for adjusting the differential and common-mode reference voltages used by the ADC to improve its linearity is described. Power dissipation is reduced by using small device sizes in the ADC and relying on calibration to cancel the large non-ideal offsets due to device mismatches. The ADC occupies 0.13 mm2 in 65 nm CMOS and dissipates 12 mW at a sample rate of 800 MS/s from a 1.2 V supply.