By Topic

Contact Resistance Reduction Technology Using Selenium Segregation for N-MOSFETs With Silicon–Carbon Source/Drain

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Hoong-Shing Wong ; Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore ; Kah-Wee Ang ; Lap Chan ; Ganesh Samudra
more authors

We report the integration of a novel selenium segregation (SeS) technology in the silicide contact of strained n-MOSFETs featuring silicon-carbon Si0.99C0.01 source/drain (S/D) stressors. SeS at the NiSi:C/n-Si0.99 C0.01 interface leads to the achievement of low Schottky barrier height and reduced silicide contact resistance R CSD. At a fixed I OFF of 100 nA/ mum, the improved silicide contact technology employing SeS contributed to a 20% drive current I ON enhancement and 30% total series resistance R Total reduction over control strained devices. The R Total improvement is primarily due to the reduction of external series resistance R EXT, which is due to a reduced R CSD at the NiSi:C/n- Si0.99C0.01 interface. Comparable DIBL, V Tsat and gate leakage density were observed for strained n-MOSFETs with or without the SeS. The impact of introducing Se in the embedded Si0.99C0.01 S/D stressor on tensile stress level in the channel region of strained n-MOSFET was also investigated.

Published in:

IEEE Transactions on Electron Devices  (Volume:56 ,  Issue: 5 )