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The high degree of freedom in the design of coarse-grained reconfigurable arrays imposes new challenges on their description and modeling. In this paper, we introduce an architecture description language targeted to describe coarse-grained reconfigurable architecture templates. It comprises innovative key features to allow fast modeling and analysis of such architectures, i.e.: representation of processing element array (ir)regularities, and flexible and concise description of interconnection network. We demonstrate that the proposed language enables a formal validation of the described template, and it eases the analysis and estimation of hardware costs earlier in the design phase. Finally, we show how we automatically generate a SystemC-based simulator of the described architecture. Our results suggest that the semantic and technical innovations of the proposed architecture description language may have a positive impact on the productivity of the design phase.