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Digital CMOS circuits are praised because of their noise immunity. However, lowering power supply voltages and shrinking device sizes, in combination with the rising electromagnetic pollution, have made this statement no longer true. An accurate behavioral model is presented for the analog simulation of digital logic circuits. The model building is automated and scalable in the sense that it allows a tradeoff between model-building speed and accuracy. The proposed model is validated on a seven-stage CMOS ring oscillator and a 112-transistor 4-bit adder, excellent test cases to demonstrate the accuracy. The RMS error remains below 5% in case of electromagnetic interference, and below 2% in all other cases, while achieving speed-ups up to 400times.