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Low density parity check (LDPC) codes are the error-correcting codes which offer huge advantages in terms of coding gain, throughput and power dissipation. Error correction algorithms are often implemented in hardware in order to ensure fast processing. The hardware implementation of LDPC decoders using traditional hardware description language (HDL) based approach is a complex and time consuming task. This paper investigates new high level approaches to design and synthesis of LDPC decoders using a combination of high level modelling tools. It compares the high level design approaches to traditional HDL-based approach. The results presented in this paper provide some useful insight into the high level design approaches, their efficiencies and possible future directions with a view to develop an efficient design and modelling framework for hardware implementation of complex LDPC decoders.