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Networks-on-Chip topology generation techniques: Area and delay evaluation

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4 Author(s)
Morgan, A.A. ; Dept. of Electr. & Comput. Eng., Univ. of Victoria, Victoria, BC ; Elmiligi, H. ; Watheq El-Kharashi, M. ; Gebali, F.

Networks-on-Chip (NoC) topology generation faces a trade-off between cost and performance. In this paper, we evaluate different custom and standard NoC topology generation techniques with respect to area and delay. The area needed for the topologies generated by these techniques is evaluated according to their routers area and number of global links. The delay is compared in terms of average internode distances. Our evaluation is done under both real and uniform traffic distributions. At the same time, we evaluate different network partitioning schemes. Kernighan-Lin (KL) partitioning is found to be the most suitable scheme for NoC topology generation. Results prove that custom topology generation techniques outperform standard techniques in terms of both area and delay. Network partitioning generation techniques result in topologies with lower area. Long-range insertion, which adds long-range links to standard mesh topology, is found to be the most delay-efficient technique.

Published in:

Design and Test Workshop, 2008. IDT 2008. 3rd International

Date of Conference:

20-22 Dec. 2008